1. Field of the Invention
The present invention relates to a load fluctuation correction circuit for correcting the source voltage supplied to a logic circuit, a timing generating circuit and a testing device including a load fluctuation correction circuit, and an electronic device including a load fluctuation correction circuit.
2. Related Art
With conventional integrated circuits and so forth, including logic circuits formed of CMOSs and so forth, the logic circuits are driven by source power received from an external circuit.
For example, an integrated circuit chip includes a power metal wiring layer connected to an external power supply via bonding wires or the like. Each logic circuit included in the integrated circuit receives source power through the power metal wiring layer thus connected to the external power supply. This means that multiple logic circuits are driven by a shared power supply.
With such a configuration, the source power applied to each logic circuit is dependent upon the driving states of other logic circuits. Specifically, the source current consumed by a logic circuit changes corresponding to the driving state of the logic circuit. The source power is supplied to the logic circuit via boding wires and a metal wiring layer as described above. Accordingly, change in the source current consumed by the surrounding logic circuits leads to change in the source voltage supplied to the logic circuit due to the resistances of the bonding wires and the metal wiring layer.
Such a logic circuit has load change characteristics in which the source voltage changes corresponding to the change in the consumed current. However, conventional techniques for correcting such change in the source voltage offer only a function of correcting low-frequency fluctuation in the source voltage.
As a technique for suppressing such a fluctuation in the source voltage, a balance circuit is known having a function of maintaining the constant source current consumed by all the circuits. The balance circuit has a mechanism as follows. That is to say, the transit time of the pulses passing through the logic circuits is detected. The current consumed by the logic circuits is calculated based upon the transit time thus detected. With the balance circuit, dummy current is consumed such that the sum of the consumed current thus calculated and the dummy current is kept at an approximately constant value as disclosed in Japanese Patent Application Publication No. 11-74768 (p. 4, FIG. 1).
However, conventional balance circuits require a great number of device components for detection of the transit time of pulses and calculation of the consumption current in the logic circuits. This leads to an increase in the scale of the circuits employed in such a conventional balance circuit. Furthermore, such great number of device components required for the aforementioned detection and calculation leads to increased overall consumption current in all circuits.